High Performance Low-Voltage Power MOSFETs with Hybrid Waffle Layout Structure in a 0.25μm Standard CMOS Process

This paper reports on a low-voltage CMOS power MOSFET layout technique, implemented in a 0.25μm, 5-metal layers CMOS process that is suitable for high speed switching power devices. The proposed hybrid waffle (HW) layout technique organizes MOSFET fingers in a square grid (waffle) arrangement. It is designed to provide an effective trade-off between the width of diagonal source/drain metal and the active device area, allowing more effective optimization between switching and conduction losses. In comparison with conventional multi-finger (MF) layouts, the HW layout is found to exhibit a 30% reduction in overall on-resistance with 3.6 times smaller total gate charge for CMOS devices with a current rating of 1A. Integrated DC-DC buck converters using HW push-pull output stages are found to have higher simulated power conversion efficiencies at switching frequencies beyond multi-MHz.